Performance Improvements of Microprocessor Platforms with a Coarse-Grained Reconfigurable Data-Path

This paper presents the performance improvements by coupling a high-performance coarse-grained reconfigurable data-path with a microprocessor in a generic platform. It is composed by computational units able to realize complex operations which aid in improving the performance of time critical application parts, called kernels. A design flow is proposed for mapping software descriptions to the microprocessor system. Analytical study is performed by mapping eight real-life applications on three different instances of the system. Significant overall application speedups, relative to a software-only solution, ranging from 1.76 to 3.88 are reported being close to theoretical speedup bounds. Key-Words: Reconfigurable computing, Coarse-grained reconfigurable data-path, Performance, Design flow, Scheduling.